Memory devices, such as synchronous memories, have a write pulse generator that may be used, along with other signals, to control the writing operations of the memory. The write pulse generator can provide discreet increments of internal write pulses that have a variable width. The variable width is controlled by optioning a number of delay elements in and out of a one shot pulse generator. The optioning can be accomplished with laser fusing or external configuration pins. However, such a configuration suffers from a limited minimum and maximum internal write pulse width when in a test mode. This limited write pulse width is generally due to the tester pulse width limitations.
The limitation of the conventional approaches is the lack of an independently functioning test mode. When in a normal mode, a limitation arises when testing of the memory is desired. It is necessary to determine what the minimum write pulse width will be when applied to the writing of the memory. The previous approaches require using fuse options or some other type of approach to vary the delay.
Referring to FIG. 1, an example of an conventional write pulse generator circuit 10 is shown. The circuit 10 comprises a register 12 and a negative edge triggered delay element 14. An external write enable signal (i.e., WEB) is presented to an input 16 of the register 12. An external clock signal (i.e., CLK) is presented to an input 18 of the register 12. An output 19 of the register 12 presents an output signal (i.e., OUT). The signal OUT is also presented to the delay block 14. The delay block 14 presents a signal to a set input 17 of the register 12. The particular amount of delay presented by the delay element 14 must generally be varied using the techniques described above (i.e., optioning, etc.)
Referring to FIG. 2, a timing diagram of the various signals of the circuit of FIG. 1 is shown. The signal CLK is shown having a positive transition 20, a negative transition 22, a positive transition 24, and a negative transition 26. The signal OUT is shown having a negative transition 28 that responds to the positive transition 20 as well as a negative transition 30 that responds to the positive transition 24. The signal OUT has a positive transition 32 and a positive transition 34 that responds to the negative transition 28 and a negative transition 30, respectively. The time difference between the negative transition 28 and the positive transition 32 is the delay defined by the delay element 14. The signal OUT has a number of positive and negative transitions that occur during the various cycles of the circuit 10.